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3 v lvds quad cmos differential line driver data sheet adn4667 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to ch ange without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2008 C 2012 analog devices, inc. all rights reserved. features 15 kv esd protection on output pins 400 mbps (200 mhz) switching rates flow through pinout simplifies pcb layout 300 ps typical differential skew 400 ps maximum differential skew 1.7 ns maximum propagation delay 3.3 v power supply 310 mv differential signaling low power dissipation (10 mw typical) interoperable with existing 5 v lvds receivers high imp edance on lvds outputs on power - down conforms to tia/eia - 644 lvds s tandard s industrial operating temperature range : ?40c to +85c available in surface - mount (soic) and low profile tssop package qualified for automotive applications applications backplane d ata t ransmission cable d ata t ransmission clock d istribution functional block diagram figure 1. general description the adn4667 is a quad, cmos, low voltage differential signaling (lvds) line driver offering data rates of over 400 mbps (200 mhz) and ultralow power consumption. it features a flow through pinout for easy pcb layout and separation of input and output signals. the device accepts low voltage ttl/cmos logic signals and convert s them to a differential current output of typically 3.1 ma for driving a transmission medium such as a twisted pair cable. the transmitted signal develops a differential voltage of typi - ca lly 310 mv across a termination resistor at the receiving end. t his is converted back to a ttl/cmos logic level by a n lvds re ceiver , such as the adn4668 . the adn4667 also offers active high and active low enable/ disable inputs (en and en ). these inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10 mw. the adn4667 and its companion lvds receiver, the adn4668 , offer a new solution to h igh speed , point - to - point data trans - mission, and a low power alternative to emitter - coupled logic (ecl) or positive emitter - coupled logic (pecl). 07032-001 adn4667 d out1+ d out1 ? d in1 d out2+ d out2 ? d in2 d out3+ d out3 ? d in3 d out4+ d out4 ? d in4 en en gnd d4 d3 d2 d1 v cc
adn4667 data sheet rev. b | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 4 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ..............................7 typical performance characteristics ..............................................8 theory of operation ...................................................................... 11 enable inputs .............................................................................. 11 applications information .......................................................... 11 outline dimensions ....................................................................... 12 ordering g uide .......................................................................... 13 automotive products ................................................................. 13 revision history 3/12 rev. a to rev. b change to features section ............................................................. 1 changes to ordering guide .......................................................... 13 added automotive products section ........................................... 13 5 /0 8 rev. 0 to rev. a added 16 - lead soic_n package .................................... universal changes to table 3 ............................................................................ 6 changes to applications information section ............................ 11 updated outline dimensions ...................................................... 11 changes to ordering guide .......................................................... 12 1/08 revision 0: initial version
data shee t adn4667 rev. b | page 3 of 16 specifications v cc = 3.0 v to 3.6 v; r l = 100 ?; c l = 15 pf to gnd; all specifications t min to t max , unless otherwise noted . all typical values are given for v cc = +3.3 v, t a = +25c . table 1 . parameter symbol min typ max unit conditions/comments 1 , 2 lvds outputs (d out+ , d out? ) differential output voltage v od 250 310 450 mv see figure 2 and figure 4 change in magnitude of v od for complementary output states v od 1 35 |mv| see figure 2 and figure 4 offset voltage v os 1.125 1.17 1.375 v see figure 2 and figure 4 change in magnitude of v os for complementary output states v os 1 25 |mv| see figure 2 and figure 4 output high voltage v oh 1.33 1.6 v see figure 2 and figure 4 output low voltage v ol 0.90 1.02 v see figure 2 and figure 4 inputs (d in , en, en ) input high voltage v ih 2.0 v cc v input low voltage v il gnd 0.8 v input high current i ih ?10 +2 +10 a v in = v cc or 2.5 v input low current i il ?10 +2 +10 a v in = gnd or 0.4 v input clamp voltage v cl ?1.5 ?0.8 v i cl = ?18 ma lvds output protection (d out+ , d out? ) output short - circuit current 3 i os ?4.2 ?9.0 ma enabled, d in = v cc , d out+ = 0 v or d in = gnd, d out? = 0 v differential output short - circuit curre nt 3 i o sd ?4.2 ?9.0 ma enabled, v od = 0 v lvds output leakage (d out+ , d out? ) power -o ff leakage i off ?20 1 +20 a v out = 0 v or 3.6 v, v cc = 0 v or o pen output three - state current i oz ?10 1 +10 a en = 0.8 v and en = 2.0 v, v out = 0 v or v cc power supply no load supply current, drivers enabled i cc 4.0 8.0 ma d in = v cc or gnd loaded supply current, drivers enabled i ccl 20 30 ma r l = 100 all channels, d in = v cc or gnd (all inputs) no load supply current, drivers disabled i ccz 2.2 6.0 ma d in = v cc or gnd, en = gnd, en = v cc esd protection d out+ , d out? 15 kv human body model all pins except d out+ , d out? 4 kv human body model 1 current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenced to ground except v od , v od , and v os . 2 the adn4667 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. typical range is 90 to 110 . 3 output short - circuit current (i os ) is specified as magnitude only ; minus sign indicates direction only.
adn4667 data sheet rev. b | page 4 of 16 ac characteristics v cc = 3.0 v to 3.6 v; r l = 100 ?; c l 1 = 15 pf to gnd; all specifications t min to t max , unless otherwise noted . all typical values are given for v cc = +3.3 v, t a = +25c. table 2 . parameter 2 min typ max unit conditions/comments 3 , 4 differential propagation delay, high to low, t phld 0.5 0.9 1.7 ns see figure 3 and figure 4 differential propagation delay , low to high, t plhd 0.5 1.2 1.7 ns see figure 3 and figure 4 differential pulse skew |t phld ? t plhd |, t skd1 5 0 0.3 0.4 ns see figure 3 and figure 4 channel -to - channel skew, t skd2 6 0 0.4 0.5 ns see figure 3 and figure 4 differential part -to - part skew, t skd3 7 0 1 .0 ns see figure 3 and figure 4 differential part -to - part skew, t skd4 8 0 1.2 ns see figure 3 and figure 4 rise time, t r 0.5 1.5 ns see figure 3 and figure 4 fall time, t f 0.5 1.5 ns see figure 3 and figure 4 disable time high to inactive, t phz 2 5 ns see figure 5 and figure 6 disable time low to inactive, t plz 2 5 ns see figure 5 and figure 6 enable time inactive to high, t pzh 3 7 ns see figure 5 and figure 6 enable time inactive to low, t pzl 3 7 ns see figure 5 and figure 6 maximum operating frequency, f max 9 200 250 mhz see figure 5 and figure 6 1 c l includes probe and jig capacitance. 2 ac parameters are guaranteed by design and characterization. 3 generator waveform for all tests unless otherwise specified: f = 50 mhz, z o = 50 , t r 1 ns, and t f 1 ns . 4 all input voltages are for one channel unless otherwise specified. other inputs are set to gnd . 5 t skd1 = |t phld ? t plhd | is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel . 6 t skd2 is the differential channel - to - channel skew of any event on the same device . 7 t skd3 , differential part - to - part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. this speci fication applies to devices at the same v cc and within 5c of each other within the operating tempe rature range. 8 t skd4 , part - to - part skew, is the differential channel - to - channel skew of any event b etween devices. this specification applies to devices over recommended operating temperature s and voltage ranges, and across process distribution. t skd4 is defined as | m ax imum ? m in imum | di fferential propagation delay. 9 f max generator input conditions: t r = t f < 1 ns (0% to 100%), 50% duty cycle, 0 v to 3 v. output c riteria: duty cycle = 45% to 55%, v od > 250 mv, all channels switching. test circuits and timing diagrams igure test circuit r drier d and igure test circuit r drier ragatin dea and transitin time 07032-002 r l /2 r l /2 d in d out+ d out ? v cc v os v od driver is enabled v v 07032-003 c l c l d in d out+ d out ? driver is enabled notes 1. c l includes load and test jig capacitance. signal generator v cc 50 ?
data sheet adn4667 rev. b | page 5 of 16 figure 4. driver propagation delay and transition time waveforms figure 5. test circuit for driver three-state delay figure 6. driver three-state delay waveforms 0 7032-004 d in v diff t plhd t phld v diff = d out+ ?d out? v oh v ol v od 3 v 1.5v 0v (differential) 0v 80% 20% 0v d out+ d out? t tlh t thl 07032-005 c l c l d out+ d out? d in signal generator 50 ? en 50 ? 50 ? 1.2v v cc en 07032-006 d out+ with d in = v cc or d out? with d in = gnd d out+ with d in = gnd or d out? with d in = v cc 3 v 1.5v 50% 50% 0v 3v 1.5v 0v v oh v ol 1.2v 1.2v en with en = gnd or open circuit en with en = v cc t pzh t phz t plz t pzl
adn4667 data sheet rev. b | page 6 of 16 absolute maximum rat ings t a = 25c, unless otherwise not ed. table 3 . parameter rating v cc to gnd ? 0.3 v to +4 v input voltage (d in ) to gnd ?0.3 v to v cc + 0.3 v enable input voltage (en, en ) to gnd ?0.3 v to v cc + 0.3 v output voltage (d out+ , d out? ) to gnd ?0.3 v to v cc + 0.3 v short - circui t duration (d out+ , d out? ) to gnd continuous industrial operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja ja thermal impedance tssop package 150.4c/w soic pack age 1 25 c/w reflow soldering peak temperature (10sec) 260c max stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. es d caution
data shee t adn4667 rev. b | page 7 of 16 pin configuration an d function descripti ons figure 7 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 en active h igh enable and power - down input (3 v ttl/cmos). if en is held low or open circuit, en enable s the drivers when high and disable s the drivers when low. 2 d in1 driver channel 1 logic input. 3 d in2 driver channel 2 logic input. 4 v cc power supply input. these parts can be operated from 3.0 v to 3.6 v . t he supply should be decoupled with a 10 f solid tantalum capacitor in parallel with a 0.1 f capacitor to gnd. 5 gnd ground reference point for all circuitry on the part. 6 d in3 drive r channel 3 logic input. 7 d in4 driver channel 4 logic input. 8 en active l ow enable and power - down input with pull - down (3 v ttl/c m o s). if en is held high, en enable s the drivers when low or open circuit and disable s the drivers and power s down the device when high. 9 d out4? channel 4 inverting output current driver. when d in4 is high, current flows into d out4? . w hen d in4 is low, current flows out of d out4? . 10 d out4+ channel 4 noni nverting output current driver. w hen d in4 is high, current flows out of d out4+ . w hen d in4 is low, current flows into d out4+ . 11 d out3+ channel 3 noninverting output current driver. when d in3 is high, current flows out of d out3+ . w hen d in3 is low, current flows into d out3+ . 12 d out3? channel 3 inverting output current driver. when d in3 is high, current flows into d out3? .w hen d in3 is low, current flows out of d out3? . 13 d out2? channel 2 inverting output current driver. when d in 2 is high, current flows into d out2 ? . w hen d in 2 is low, cur rent flows out of d out 2 ? . 14 d out2+ channel 2 non inverting output current driver. when d in2 is high, current flows out of d out2+ . w hen d in2 is low, current flows into d out2+ . 15 d out1+ channel 1 noninverting output current driver. when d in1 is high, curr ent flows out of d out1+ . w hen d in1 is low, current flows into d out1+ . 16 d out1? channel 1 inverting output current driver. when d in 1 is high, current flows into d out1? . w hen d in1 is low, current flows out of d out1? . 07032-007 nc = no connect 1 2 3 4 5 6 7 8 d in1 d in2 v cc d in4 d in3 gnd en en 16 15 14 13 12 1 1 10 9 d out1 + d out2 + d out2 ? d out4 + d out4 ? d out3 + d out3 ? d out1 ? adn4667 t op view (not to scale)
adn4667 data sheet rev. b | page 8 of 16 typical performance characte ristics figure 8 . output high voltage v s. power supply voltage figure 9 . ou tput low voltage v s. power supply voltage figure 10 . output short - circuit current v s. power supply voltage figure 11 . output three - state current v s. power supply voltage figure 12 . differential output voltage v s. power supply voltage figure 13 . differential output voltage v s. load resistor 07032-008 1.415 1.414 1.413 1.412 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output high voltage, v oh ( v) power supply voltage, v cc (v) t a = 25c r l = 100 ? 07032-009 1.090 1.089 1.088 1.087 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output low voltage, v ol ( v) power supply voltage, v cc (v) t a = 25c r l = 100 ? 07032-010 ? 3.9 ? 4.0 ? 4.1 ? 4.2 3.0 3.1 3.2 3.3 3.4 3.5 3.6 short-circuit current, i os (m a) power supply voltage, v cc (v) t a = 25c v in = gnd or v cc v out = 0v 07032-011 440 360 380 400 420 340 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output three-state current, i oz (pa) power supply voltage, v cc (v) t a = 25c v in = gnd or v cc 07032-012 325.0 324.2 324.4 324.6 324.8 324.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 differential output voltage, v od (mv) power supply voltage, v cc (v) t a = 25c r l = 100 ? 07032-013 500 300 350 400 450 250 90 100 110 120 130 140 150 differential output voltage, v od (mv) load resistor, r l ( ?) t a = 25c v cc = 3.3 v
data shee t adn4667 rev. b | page 9 of 16 figure 14 . offset voltage v s. power supply voltage figure 15 .power supply current v s . switching frequency figure 16 . power supply current v s. power supply voltage figure 17 . power supply current v s . ambient temperature figure 18 . differential propagation delay v s. power supply voltage figure 19 . differential propagation delay v s . ambient temperature 07032-014 1.252 1.250 1.251 1.249 3.0 3.1 3.2 3.3 3.4 3.5 3.6 offset voltage, v os (mv) power supply voltage, v cc ( v) t a = 25c r l = 100 ? 07032-015 26 16 18 20 22 24 14 0.1 1 10 100 500 power supply current, i cc (ma) switching frequency ( mhz ) t a = 25c c l = 15 pf v cc = 3.3v v in = 0v to 3v r l = 100 ? per driver all channels switching one channel switching 07032-016 14.925 14.915 14.920 14.910 3.0 3.1 3.2 3.3 3.4 3.5 3.6 power supply current, i cc (ma) power supply voltage, v cc ( v) t a = 25c f = 1mhz c l = 15pf v in = 0v to 3v r l = 100 ? per driver 07032-017 14.92 14.89 14.90 14.91 14.88 ?40 ?20 0 20 40 60 80 100 power supply current, i cc (ma) ambient temperature, t a ( c ) v cc = 3.3v f = 1mhz c l = 15pf v in = 0v to 3v r l = 100 ? per driver 07032-018 1200 1000 1 100 900 3.0 3.1 3.2 3.3 3.4 3.5 3.6 differential propagation delay (ns) power supply voltage, v cc ( v) t phld t plhd t a = 25c f = 1mhz c l = 15pf r l = 100 ? per driver 07032-019 1200 1000 1 100 900 differential propagation delay (ns) ambient temperature, t a ( c ) t phld t plhd ?40 ?20 0 20 40 60 80 100 v cc = 3.3v f = 1mhz c l = 15pf r l = 100 ? per driver
adn4667 data sheet rev. b | page 10 of 16 figure 20 . differential skew v s. supply voltage figure 21 . differential skew v s . ambient temperature figure 22 . transition time v s . supply voltage figure 23 . transition time v s . ambient temperature 07032-020 100 20 40 60 80 0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 differential skew, t skd (ps) power supply voltage, v cc ( v) t a = 25c f = 1mhz c l = 15pf r l = 100 ? per driver 07032-021 50 10 20 30 40 0 differential skew, t skd (ps) ambient temperature, t a ( c ) ?40 ?20 0 20 40 60 80 100 v cc = 3.3v f = 1mhz c l = 15pf r l = 100 ? per driver 07032-022 400 340 360 380 320 3.0 3.1 3.2 3.3 3.4 3.5 3.6 transition time (ps) power supply voltage, v cc ( v) t a = 25c f = 1mhz c l = 15pf r l = 100 ? per driver t tlh t thl 07032-023 400 340 360 380 320 transition time (ps) ambient temperature, t a ( c ) ?40 ?20 0 20 40 60 80 100 t tlh t thl v cc = 3.3v f = 1mhz c l = 15pf r l = 100 ? per driver
data sheet adn4667 rev. b | page 11 of 16 theory of operation the adn4667 is a quad line driver for low voltage differential signaling. it takes a single-ended 3 v logic signal and converts it to a differential current output. the data can then be trans- mitted for considerable distances, over media such as a twisted pair cable or pcb backplane, to an lvds receiver like the adn4668, where it develops a voltage across a terminating resistor, r t . this resistor is chosen to match the characteristic impedance of the medium, typically around 100 . the differential voltage is detected by the receiver and converted back into a single-ended logic signal. when d in is high (logic 1), current flows out of the d out+ pin (current source) through r t and back into the d out? pin (current sink). at the receiver, this current develops a positive differential voltage across r t (with respect to the inverting input) and gives a logic 1 at the receiver output. when d in is low, d out+ sinks current and d out? sources current; a negative differen- tial voltage across r t gives a logic 0 at the receiver output. the output drive current is between 2.5 ma and 4.5 ma (typically 3.1 ma), developing between 250 mv and 450 mv across a 100 termination resistor. the received voltage is centered around the receiver offset of 1.2 v. therefore, the noninverting receiver input is typically (1.2 v + [310 mv/2]) = 1.355 v, and the inverting receiver input is (1.2 v ? [310 mv/2]) = 1.045 v for logic 1. for logic 0, the inverting and noninverting output voltages are reversed. note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across r t is twice the differential voltage. current mode drivers offer considerable advantages over voltage mode drivers such as rs-422 drivers. the operating current remains fairly constant with increased switching frequency, whereas that of voltage mode drivers increase exponentially in most cases. this is caused by the overlap as internal gates switch between high and low, which causes currents to flow from the device power supply to ground. a current mode device simply reverses a constant current between its two outputs, with no significant overlap currents. this is similar to emitter-coupled logic (ecl) and positive emitter-coupled logic (pecl), but without the high quiescent current of ecl and pecl. enable inputs the active high and active low enable inputs deactivate all the current drivers when in the disabled state. this also powers down the device and reduces the current consumption from typically 20 ma to typically 2.2 ma. a truth table for the enable inputs is shown in table 5. table 5. enable inputs truth table en en d in d out+ d out? h l or open l i sink i source h l or open h i source i sink any other combination of en and en x inactive inactive applications information figure 24 shows a typical application for point-to-point data transmission using the adn4667 as the driver and the adn4668 as the receiver. figure 24. typical application circuit 07032-024 d in d out+ d out? r in+ r in? r t 100 ? en en d out en en 1/4 adn4667 1/4 adn4668 gnd gnd
adn4667 data sheet rev. b | page 12 of 16 outline dimensions figure 25 . 16 - lead standard small outline package [so ic_n] narrow body (r - 16) dimensions shown in millimeters and (inches) figure 26 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc sea ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 060606- a 45 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab
data shee t adn4667 rev. b | page 13 of 16 ordering guide model 1 , 2 temperature range package description package option adn4667arz ? 40c to +85c 16 - lead standard small outline package [soic_n] r -16 adn4667arz - reel7 ? 40c to +85c 16 - lead standard small outline package [soic_n] r -16 adn4667aruz ?40c to +85c 16 - lead thin shrink small outline package [tssop] ru -16 adn4667aruz - reel7 ?40c to +85c 16 - lead thin shrink small outline package [tssop] ru -16 adn4667warz - reel7 ? 40c to +85c 16 - lead standard small outline package [soic_n] r -16 1 z = rohs compliant part . 2 w = qualified for automotive applications automotive products the adn4667w model is available with controlled manufacturing to support the quality and reliability requirements of automoti ve applications. note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade product shown is available for use in automotive applications. contact your local analo g devices account representative for specific product ordering information and to obtain the specific automoti ve reliability reports for this model .
adn4667 data sheet rev. b | page 14 of 16 notes
data shee t adn4667 rev. b | page 15 of 16 notes
adn4667 data sheet rev. b | page 16 of 16 notes ? 2008 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07032 - 0 - 3/12(b)

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